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Infineon Technologies CY7C425-10JXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C425-10JXC Infineon 9K Async FIFO 50 MHz 10 ns 32-PLCC

MPNCY7C425-10JXC
Obsolete

Infineon CY7C425-10JXC, 9K (1K x 9) asynchronous FIFO, 50 MHz data rate, 10 ns access time, 4.5–5.5 V supply, 32-PLCC (J-lead), 0–70 °C.

Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C425-10JXC specifications
ParameterValue
SeriesCY7C
MountingSurface Mount
Expansion typeDepth, Width
Voltage4.5 V ~ 5.5 V
Current - supply85mA
Operating temperature0°C~70°C
PackageTube
FunctionAsynchronous
Data rate50MHz
Access time10ns
Memory size9K (1K x 9)
FWFT supportNo
Case32-LCC (J-Lead)
Bus directionalUni-Directional
Retransmit capabilityYes
Programmable flags supportNo

Product details

Asynchronous FIFO with 10 ns access — what the speed rating buys you

The CY7C425-10JXC is a 9K (1K x 9) asynchronous FIFO from the CY7C series, rated at 50 MHz data rate with a 10 ns access time. The 9-bit width (1K x 9) includes a ninth bit often used for parity or a control flag.

No official successor or second-source is listed. Production has ended; new orders are fulfilled from remaining distributor stock or the spot market. For a BOM line that still specifies this exact order code, procurement must go through independent distribution or a broker. Date codes and package condition (tube, not tape/reel) vary — confirm the visual and electrical quality before ordering.

Retransmit capability and expansion options

Retransmit capability allows the FIFO to re-present data from the first location without a full reset and rewrite — useful for retry protocols or data replay in test equipment. The part supports depth and width expansion for cascading multiple devices, though the asynchronous nature means careful timing on the expansion control signals. No FWFT (First-Word Fall-Through) support means the first word written does not appear on the outputs until a read cycle is issued — the output register holds the previous word until the read flag toggles. No programmable flags — the empty and full flags are fixed thresholds determined by the internal write and read pointers.

Frequently asked questions

Does the CY7C425-10JXC work at 5V?

Yes. All inputs and outputs are 5 V tolerant. No level shifting needed when interfacing with other 5 V logic families.

What is the data rate and access time of the CY7C425-10JXC?

The maximum data rate is 50 MHz, and the access time is 10 ns. The 10 ns access time is the read-access window; at 50 MHz the cycle period is 20 ns, leaving 10 ns for data setup at the receiving device. The part can sustain back-to-back reads at full speed if the read enable timing is clean.