Obsolete FIFO — sourcing through independent channels
The CY7C421-20VXC: This part is sourced to order against an RFQ through independent surplus channels.
Memory organization and key timing
The CY7C421-20VXC is a 4.5K (512 x 9) asynchronous FIFO memory. The 9-bit width supports parity or control bit alongside the data byte, common in datacom and telecom buffer applications. Access time is 20 ns, and the maximum data rate is 50 MHz. The 20 ns access time sets the read-cycle floor — the downstream logic must latch data within that window after the read-enable edge.
Supply, temperature, and package
Housed in a 28-SOJ (Small Outline J-Lead) package, 0.300-inch body width, 7.62 mm. The J-lead footprint saves board space compared to a DIP but requires a reflow solder profile compatible with SOIC-28 land patterns.