The CY7C2565KV18-400BZXC is a 72 Mbit synchronous SRAM using QDR II+ architecture, organized 2M x 36. The 400 MHz clock rate delivers back-to-back read and write transactions on separate buses — no dead cycles between reads and writes, which is the whole point of QDR. This part lives in high-bandwidth look-aside buffer applications: network processors, high-end FPGAs, and ASICs where the memory interface needs to keep up with a 36-bit data bus without bus-turnaround penalties. Supply voltage range is 1.7V to 1.9V, which puts it in the 1.8V nominal SRAM class — check your FPGA I/O bank voltage before committing.
Package and temperature — footprint and environment limits
Housed in a 165-ball FBGA measuring 13x15 mm (supplier device package 165-FBGA). The 0.80 mm ball pitch is typical for this density; fan-out on a four-layer board is straightforward, but verify the ball-out against your FPGA footprint.
Infineon lists the CY7C2565KV18-400BZXC as Obsolete. For existing designs, the only sourcing path is through independent distribution or the spot market.