QDR II+ synchronous SRAM — 72Mbit at 400 MHz
The Infineon CY7C25652KV18-400BZI is a 72Mbit synchronous SRAM organized as 2M x 36, using the QDR II+ (Quad Data Rate II+) interface. The 400 MHz clock rate delivers four data transfers per clock cycle — two reads and two writes per cycle — giving a peak bandwidth of 3.2 Gbytes/s on the x36 bus. This part is volatile SRAM, formatted as standard SRAM with a parallel memory interface.
The 0.80 mm ball pitch and the 13x15 mm body footprint dictate the PCB escape routing — a 4-layer board with microvias is typical for fanning out the 165 balls at this pitch. The supply voltage range (1.7V to 1.9V) means the core rail must be regulated to within ±100 mV. Decoupling capacitance placement close to the FBGA balls is critical to keep supply noise below the 100 mV peak-to-peak that the QDR II+ I/O tolerates.
Lifecycle and procurement reality
Infineon has placed the CY7C25652KV18-400BZI into Last Buy status — this is the final procurement window before permanent discontinuation. Available through independent distribution channels.