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Infineon Technologies CY7C2263XV18-633BZXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C2263XV18-633BZXC SRAM, 36 Mbit QDR II+, 633 MHz

MPNCY7C2263XV18-633BZXC
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Cypress CY7C2263XV18-633BZXC, QDR II+ synchronous SRAM, 36 Mbit (2M x 18), 633 MHz clock, parallel interface, 1.7 V–1.9 V supply, 165-ball FBGA (13x15 mm), commercial temperature 0°C to 70°C, tray.

$100.8125Ref. price · indicative, final on quote
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C2263XV18-633BZXC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage1.7V ~ 1.9V
Frequency633 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, QDR II+
Memory size36Mbit
Memory formatSRAM
Case165-LBGA
Memory organization2M x 18

Product details

The 165-ball FBGA package (13x15 mm body) is surface-mount only. This part targets high-bandwidth buffering in networking equipment, test instrumentation, and telecom line cards where back-to-back read-write throughput without dead cycles is critical.

633 MHz clock — throughput and timing margin

The 633 MHz clock rate defines the peak data rate for the QDR II+ interface. Each clock edge transfers data on both rising and falling edges, so the effective I/O bandwidth is double the clock frequency.

The 165-ball FBGA (13x15 mm) is a fine-pitch BGA. It requires a multi-layer PCB with microvias or blind vias for breakout, plus X-ray inspection after reflow. The tray shipping medium means the parts arrive in antistatic trays, not tape-and-reel — factor that into pick-and-place feeder setup if you're running high-volume assembly.

Frequently asked questions

What is the memory organization of CY7C2263XV18-633BZXC?

The memory is organized as 2M words by 18 bits, for a total of 36 Mbit. The 18-bit word width supports parity or ECC schemes in a single chip.