Infineon lists the CY7C199NL-15ZXCT as Obsolete. For BOM lines that still require this specific SRAM, independent distribution is the practical channel. We source per RFQ against your target quantity — no stock-holding claim, confirmed at quote time.
15 ns access time, 32K x 8 organization
This is a 256Kbit asynchronous SRAM organized as 32K words by 8 bits. The 15 ns access time sets the read-cycle floor for the bus — the parallel interface latches data on the address-to-output delay, not a clock edge. The write cycle time matches the read at 15 ns, so back-to-back writes keep the bus at full throughput without wait states.
28-TSSOP footprint, commercial temp
Housed in a 28-TSSOP package (0.465", 11.80 mm width), with the supplier device package listed as 28-TSOP I. The 0.65 mm pitch is a standard footprint for 8-bit SRAMs — the same land pattern fits many 32K x 8 parts.