20 ns async SRAM for legacy 5 V bus systems
The CY7C199C-20VXC: Housed in a 28-SOJ surface-mount package, this part is a drop-in for legacy 5 V processor and DSP designs that need fast, byte-wide scratchpad or look-up table memory without the overhead of a synchronous clock.
Obsolete — plan for a last-time buy or surplus channel
Infineon lists the CY7C199C-20VXC as Obsolete. For production builds, this means new- and surplus-stock procurement through independent distribution is the only channel. If the BOM still calls for this exact footprint and timing, secure inventory now — the surplus pool shrinks as existing stocks are consumed.
In a 5 V system with a 50 MHz bus (20 ns period), this leaves zero margin for address decoding, trace delay, and setup time at the processor — so this part is really suited to 25–33 MHz buses where you have 10–15 ns of slack.