256Kbit asynchronous SRAM in a 28-SOJ package
The CY7C199-35VC: Housed in a 28-SOJ surface-mount package, this part was designed for legacy 5V logic systems requiring fast, byte-wide static RAM — think 8-bit microcontroller data buffers, cache tag stores, or industrial controller local memory where a 35 ns cycle matches the bus timing of older processors.
35 ns access time — bus timing margin
The 35 ns access time and write cycle time match the bus timing of older processors.
5V supply — legacy logic compatibility
It will work directly with 5V TTL or CMOS logic without level shifters. If you're retrofitting a board that originally used a 5V SRAM, this is the right voltage domain. Do not run it at 3.3V — the minimum is 4.5V.
Obsolete — plan your sourcing accordingly
If you have a production run that depends on this SRAM, consider qualifying a pin-compatible alternative now to avoid a future supply gap.