For BOM positions that still need this exact order code, supply is limited to independent-distribution inventory — sourced and quoted per RFQ against the exact quantity.
15 ns access time — timing margin for legacy bus
This is a 64Kbit asynchronous SRAM organized as 8K x 8 with a 15 ns access time and a matching 15 ns write cycle time. The 15 ns figure sets the minimum read-cycle window on the parallel bus — a legacy 5 V controller with a 20 ns or slower memory interface has comfortable margin; a faster bus (10 ns or below) will see setup violations without wait states.
28-SOJ package — footprint check
Housed in a 28-SOJ (Small Outline J-lead) package, 0.300-inch body width, 7.62 mm. The J-lead footprint is distinct from a standard SOIC — the bent leads tuck under the body, saving board area but requiring a specific solder-paste stencil aperture. Confirm the existing PCB land pattern matches the 28-SOJ mechanical drawing before committing.