72 Mbit QDR II SRAM at 400 MHz — what this part is
The Infineon (formerly Cypress) CY7C1565V18-400BZXC is a 72 Mbit synchronous QDR II SRAM organized as 2M x 36, clocked at 400 MHz with a parallel interface. QDR II (Quad Data Rate) architecture delivers two read and two write data words per clock cycle, giving this part a peak bandwidth of 28.8 Gbit/s on a single 1.8 V supply rail. It is built for high-throughput, low-latency lookup and buffering in networking switches, routers, telecom line cards, and test equipment where SRAM speed and deterministic access matter more than DRAM density.
At 400 MHz, the QDR II interface transfers data on both rising and falling edges of the clock, so the effective data rate per pin is 800 Mbps. For a 36-bit-wide data bus, that translates to 28.8 Gbps aggregate bandwidth. The 2M x 36 organization means a single chip can hold 2 million 36-bit words — enough for a large forwarding table or a deep packet buffer in a 10/25 GbE line card.
Cypress (now Infineon) has discontinued production, and no factory orders or last-time-buy windows remain open.
165-FBGA — board-level reality
The 165-ball FBGA package measures 15 x 17 mm with a 1.0 mm ball pitch. Surface-mount only, no through-hole option.