72 Mbit QDR II+ SRAM at 400 MHz — bus bandwidth for packet buffers
Its 400 MHz clock rate delivers back-to-back read/write throughput without the dead cycles that older NoBL or DDR SRAMs impose — a direct fit for high-bandwidth network buffers, line cards, and FPGA-based packet-processing engines where every bus cycle counts.
Package and mounting — 165-FBGA (13x15 mm)
The fine-pitch BGA requires a multi-layer PCB with microvias or blind vias for signal breakout.
