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Infineon Technologies CY7C1563V18-400BZC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1563V18-400BZC Infineon 72Mbit QDR II SRAM, 400 MHz

MPNCY7C1563V18-400BZC
Obsolete

Infineon Technologies CY7C1563V18-400BZC, QDR II synchronous SRAM, 72 Mbit, 4M x 18 organization, 400 MHz clock, 1.7V-1.9V supply, 165-FBGA, tray.

Infineon Technologies CY7C1563V18-400BZC datasheet (PDF)
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1563V18-400BZC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage1.7V ~ 1.9V
Frequency400 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, QDR II
Memory size72Mbit
Memory formatSRAM
Case165-LBGA
Memory organization4M x 18

Product details

72 Mbit QDR II — 400 MHz clock, 4M x 18 organization

The CY7C1563V18-400BZC is a 72 Mbit QDR II synchronous SRAM organized as 4M x 18 bits, clocked at 400 MHz. The QDR II architecture delivers separate read and write data ports on each clock edge — two read and two write transactions per cycle — so the 400 MHz clock yields an effective 800 MHz data rate on each port. The 1.7 V to 1.9 V core supply keeps I/O power low, but the 165-ball FBGA (15x17 mm) demands a controlled-impedance layout on the data and address lines to maintain signal integrity at those edge rates.

Sourcing runs through independent distribution — quantities are lot-specific and confirmed at RFQ.

Supplied in tray packaging, the part is a surface-mount 165-LBGA with a supplier device package of 165-FBGA measuring 15x17 mm.

Frequently asked questions

What is the memory organization and clock speed?

4M x 18 bits at a 400 MHz clock. The QDR II architecture transfers data on both clock edges, so the effective data rate on each port is 800 MT/s.