QDR II SRAM at 300 MHz — bus architecture note
That eliminates the bus-turnaround dead cycles you get with common I/O SRAM, so back-to-back read-write throughput stays at the full 300 MHz rate. Organized as 2M x 36, it targets high-bandwidth data buffers in network switches, line cards, and test equipment where latency consistency matters more than raw density.
Obsolete — sourcing reality for this BOM line
The part ships in a 165-ball FBGA (15x17 mm body), surface-mount only.
