QDR II SRAM for high-throughput buffer applications
It operates at a 300 MHz clock, delivering a peak data rate of 600 MHz on the data bus through separate read and write ports. This part is designed for high-bandwidth, low-latency buffer applications typical in networking switches, routers, and telecom line cards where back-to-back transactions without dead cycles are required.
At 300 MHz, each port (read and write) transfers data on both clock edges, so the effective data rate per port is 600 million transfers per second. With an 18-bit bus, the raw throughput approaches 10.8 Gbps aggregate. The QDR II architecture eliminates the bus-turnaround dead cycles that plague common I/O SRAMs, so back-to-back read and write operations sustain that rate. This makes the part a natural fit for packet buffers, lookup tables, and queue managers in line-rate Ethernet or ATM equipment.