Infineon CY7C1512KV18-300BZC, QDR II synchronous SRAM, 72Mbit (4M x 18), 300 MHz clock, 1.7V–1.9V supply, 165-FBGA (13x15), 0°C to 70°C, Tray.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting type | Surface Mount |
| Voltage | 1.7V ~ 1.9V |
| Frequency | 300 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, QDR II |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 4M x 18 |
The CY7C1512KV18-300BZC is a 72 Mbit synchronous SRAM built on the QDR II architecture, organized as 4M x 18. It clocks at 300 MHz.
At 300 MHz, the QDR II architecture clocks data on both edges. The parallel interface keeps latency deterministic.
Yes, Infineon has classified this part as Last Buy. The manufacturer's final production run is underway; after the LTB cutoff date, no new factory orders will be accepted. Sourcing now through independent distribution is the path to secure inventory.
No official replacement or successor order code is listed in the available records. For a pin-compatible alternative, the CY7C1512KV18-300BZX shares the same base product number and QDR II architecture — verify the suffix differences against the datasheet before substituting. If a direct drop-in is required, the best approach is to source remaining Last Buy stock.
This part is sourced to order against an RFQ through independent distribution. Availability and current pricing are confirmed at quote time. No stock count or lead-time number is published here because the supply position changes daily as Last Buy inventory is consumed.
It is a QDR II synchronous SRAM with 72 Mbit density organized as 4M x 18. The QDR II architecture uses separate read and write data ports to eliminate bus-turnaround dead cycles, making it suitable for high-throughput applications like network packet buffers and FPGA cache.