72 Mbit QDR II SRAM — 300 MHz bus performance for high-throughput designs
It clocks at 300 MHz.
At 300 MHz, the QDR II architecture clocks data on both edges. The parallel interface keeps latency deterministic.
Infineon CY7C1512KV18-300BZC 72Mbit QDR II SRAM, 300 MHz
MPNCY7C1512KV18-300BZC
Last Buy
Infineon CY7C1512KV18-300BZC, QDR II synchronous SRAM, 72Mbit (4M x 18), 300 MHz clock, 1.7V–1.9V supply, 165-FBGA (13x15), 0°C to 70°C, Tray.
$119.7600Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026
Specifications
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 1.7V ~ 1.9V |
| Clock frequency | 300 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, QDR II |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 4M x 18 |
Product details
Frequently asked questions
Is CY7C1512KV18-300BZC obsolete or last buy?
Yes, Infineon has classified this part as Last Buy. The manufacturer's final production run is underway; after the LTB cutoff date, no new factory orders will be accepted. Sourcing now through independent distribution is the path to secure inventory.
What is the replacement or equivalent for CY7C1512KV18-300BZC?
No official replacement or successor order code is listed in the available records. For a pin-compatible alternative, the CY7C1512KV18-300BZX shares the same base product number and QDR II architecture — verify the suffix differences against the datasheet before substituting. If a direct drop-in is required, the best approach is to source remaining Last Buy stock.
Where can I buy CY7C1512KV18-300BZC and what is the stock status?
This part is sourced to order against an RFQ through independent distribution. Availability and current pricing are confirmed at quote time. No stock count or lead-time number is published here because the supply position changes daily as Last Buy inventory is consumed.
What is CY7C1512KV18-300BZC's technology and memory organization?
It is a QDR II synchronous SRAM with 72 Mbit density organized as 4M x 18. The QDR II architecture uses separate read and write data ports to eliminate bus-turnaround dead cycles, making it suitable for high-throughput applications like network packet buffers and FPGA cache.