6.5 ns access time — what it means for the bus
The CY7C1481BV33-133BZXC has a 6.5 ns access time and a 133 MHz clock. The access time is the delay from address assertion to valid data output on the parallel bus.
Cypress CY7C1481BV33-133BZXC 72Mbit Sync SRAM, 133 MHz, 6.5 ns
MPNCY7C1481BV33-133BZXC
Obsolete
Cypress CY7C1481BV33-133BZXC, 72Mbit Synchronous SRAM, 133 MHz clock, 6.5 ns access time, 2M x 36 organization, 3.135V–3.6V supply, 0°C to 70°C, 165-FBGA (15x17 mm), Tray.
$190.7800Ref. price · indicative, final on quote
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MOQ1 pcs
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
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Specifications
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting type | Surface Mount |
| Voltage | 3.135V ~ 3.6V |
| Frequency | 133 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, SDR |
| Access time | 6.5 ns |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 2M x 36 |
Product details
Frequently asked questions
Is CY7C1481BV33-133BZXC obsolete?
Yes, the CY7C1481BV33-133BZXC is obsolete. Cypress has discontinued production; there is no official replacement listed. Sourcing is through surplus and broker channels.
What is the replacement for CY7C1481BV33-133BZXC?
No direct pin-compatible replacement is listed in the official record. Any substitute must be evaluated for timing, organization, and package compatibility — the 2M x 36 organization and 133 MHz / 6.5 ns timing are specific to this speed grade.
What is the access time of CY7C1481BV33-133BZXC?
The access time is 6.5 ns, paired with a 133 MHz clock. This is the time from address assertion to valid data output on the parallel bus.
Is CY7C1481BV33-133BZXC compatible with 3.3V logic?
Yes, the supply range is 3.135V to 3.6V, making it compatible with 3.3V nominal logic families. I/O levels are 3.3V.