Cypress NoBL CY7C1472BV33-200BZXC, 72Mbit synchronous SDR SRAM, 4M x 18 organization, 200 MHz clock, 3 ns access time, 3.3 V supply, 165-LBGA (15x17) in tray, 0°C to 70°C.
| Parameter | Value |
|---|---|
| Series | NoBL™ |
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 3.135V ~ 3.6V |
| Clock frequency | 200 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, SDR |
| Access time | 3 ns |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 4M x 18 |
The Cypress CY7C1472BV33-200BZXC is a 72 Mbit synchronous SRAM organized 4M x 18, built on the NoBL (No Bus Latency) architecture. It runs at a 200 MHz clock with a 3 ns access time, meaning the pipeline can deliver back-to-back reads or writes without inserting dead cycles — a trait that matters when your bus is the bottleneck in a high-throughput buffer, cache, or FIFO application.
This limits the part to indoor, climate-controlled equipment.
It is organized as 4M words by 18 bits (4M x 18), giving a total of 72 Mbit. The 18-bit word width suits 16-bit data buses with two parity/ECC bits.