Infineon NoBL™ synchronous SRAM, CY7C1471V33-117AXC, 72Mbit organized 2M x 36, 117 MHz clock, 7.5 ns access, 3.135V–3.6V supply, parallel interface, 100-LQFP tray, 0°C–70°C.
| Parameter | Value |
|---|---|
| Series | NoBL™ |
| Memory type | Volatile |
| Mounting type | Surface Mount |
| Voltage | 3.135V ~ 3.6V |
| Frequency | 117 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, SDR |
| Access time | 7.5 ns |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 100-LQFP |
| Memory organization | 2M x 36 |
The 117 MHz clock rate and 7.5 ns access time define bus timing closure. The NoBL architecture eliminates dead cycles between reads and writes.
The CY7C1471V33-117AXC is marked obsolete by Infineon. There is no official successor order code for this speed and temperature grade.
This obsolete part is sourced and quoted to order through our independent distribution network. Submit an RFQ with your target quantity; we confirm availability and current pricing at quote time. No stock or lead-time figures are published because supply is lot-by-lot.
No official pin-compatible alternative is listed in the lifecycle record for this specific speed grade (117 MHz) and temperature range (0°C to 70°C). The NoBL family includes other density and speed variants, but without a confirmed cross-reference, any substitution requires a full timing and footprint validation against your design.
It is organized as 2M words by 36 bits, for a total of 72 megabits. The 36-bit width is typical for designs that combine a 32-bit data bus with 4 bits of parity or ECC.