72Mbit NoBL synchronous SRAM — 167 MHz, 3.4 ns access
The CY7C1470BV33-167BZIT: 72Mbit synchronous SRAM organized as 2M x 36, NoBL architecture. Clocks at 167 MHz with 3.4 ns access time.
NoBL architecture — what it means for bus throughput
NoBL means the SRAM can switch from a read to a write on consecutive clock cycles without inserting a dead cycle. At 167 MHz, that saves one clock per transaction — a meaningful gain in systems that mix reads and writes on the same bus, like packet buffers or shared-memory multiprocessor designs. A conventional synchronous SRAM would stall for one cycle on every read-to-write transition; this part does not.
End-of-life — plan the last-time-buy now
This part is flagged end-of-life (eol_hot). Buyers should secure final quantities through independent distribution.