72 Mbit NoBL synchronous SRAM — 167 MHz, 3.4 ns access
The CY7C1470BV25-167BZIT runs at a 167 MHz clock frequency with a 3.4 ns access time.
The NoBL™ architecture allows the SRAM to accept a new bus command on every clock cycle, even when the previous operation is still completing. For a 167 MHz interface, this means back-to-back reads and writes without inserting idle cycles for bus turnaround. The 3.4 ns access time gives the controller enough setup-and-hold margin at that clock rate, which is critical for timing closure in high-throughput designs like network packet buffers or telecom line cards.
The 2.375 V to 2.625 V supply range aligns with 2.5 V logic families common in FPGA and ASIC interfaces on those boards.
The CY7C1470BV25-167BZIT carries an official lifecycle status of Obsolete. Buyers should verify stock position and lead time with a distributor.