For existing BOM lines, supply runs through the independent surplus and broker channel — expect to quote against available inventory rather than factory order.
250 MHz clock, 2.5 ns access — the throughput story
This is a NoBL (No Bus Latency) synchronous SRAM from Cypress, organized as 2M x 18 bits for a total of 36 Mbit. The 250 MHz clock frequency and 2.5 ns access time mean back-to-back read/write cycles with zero dead cycles on the bus — critical for high-throughput data buffers in network switches, telecom line cards, or test equipment where every clock edge counts. The parallel memory interface and 2.375V to 2.625V supply range align with 2.5V logic families.
Package and footprint — 165-FBGA (15x17 mm)
Housed in a 165-ball FBGA (15x17 mm) package, surface-mount only. The fine-pitch BGA requires controlled reflow profiles and X-ray inspection for solder joint integrity.
