36Mbit NoBL synchronous SRAM at 250 MHz
It clocks at 250 MHz with a 2.6 ns access time, operating from a 3.135V to 3.6V supply. The NoBL architecture eliminates the dead cycle between read and write operations, sustaining full bus throughput on back-to-back transactions — useful in high-bandwidth data buffers, network switches, and telecom line cards where every clock cycle counts.
At 250 MHz the clock period is 4 ns. The 2.6 ns access time leaves 1.4 ns of setup/hold margin for the controller, which is tight but workable with careful PCB routing. The 36-bit wide data bus (1M x 36) moves 9 bits per clock per byte lane, so a single burst can shift 36 bits every cycle. This part is sized for designs that need sustained read-write throughput without wait states — think packet buffers, CAM tables, or DSP coefficient storage where the NoBL flow-through keeps the pipeline full.
Cypress lists the CY7C1460AV33-250AXI as Obsolete. If your design can tolerate a different package or density, a cross-ship evaluation against the wider NoBL family may open alternatives, but no pin-compatible drop-in is documented here.