36 Mbit NoBL synchronous SRAM — what this part is
The NoBL architecture eliminates the dead cycle normally required when switching between read and write operations on the same bus, allowing back-to-back transactions without wait states.
250 MHz clock and 2.6 ns access — the timing budget
The 250 MHz clock rate and 2.6 ns access time are the headline specs that determine whether this SRAM can keep up with a high-speed processor or FPGA memory port. At 250 MHz, the bus cycles every 4 ns; the 2.6 ns access means the data appears on the outputs within that window, leaving about 1.4 ns of setup/hold margin for the controller. That margin shrinks with trace delay and clock skew, so the PCB layout needs matched-length traces and clean supply decoupling to hold timing closure. The NoBL feature means you don't lose a cycle on read-to-write or write-to-read turns — the bus stays full every clock edge, which is the difference between sustaining 250 MHz throughput and dropping to an effective 125 MHz on a mixed-transaction workload.
Package and footprint — 100-TQFP
The package is rated for surface-mount assembly only. The Tape & Reel suffix (AXCT) indicates it ships on 13-inch reels, typically 1000 pieces per reel for this package size.