36 Mbit NoBL synchronous SRAM for high-throughput buffering
The 167 MHz clock rate and 3.4 ns access time together define the part's timing budget. The NoBL architecture allows a new bus transaction every clock cycle without idle cycles for read-to-write or write-to-read transitions. For the designer, this means the memory controller can sustain full-rate throughput without bus-turnaround penalties, which is the primary reason to choose this part over a standard synchronous SRAM. The 3.4 ns access is the time from clock edge to valid data out; at 167 MHz (6 ns cycle), the access comfortably fits within one cycle with margin for PCB trace delay.
Obsolete — lifecycle and sourcing reality
For new designs, Infineon does not list a direct drop-in successor; any replacement will require a re-qualification of the SRAM footprint and timing. For existing BOMs, buyers should secure remaining stock or plan a last-time-buy strategy.
Package and temperature — board-fit checklist
The part comes in a 100-LQFP package (supplier device package 100-TQFP, 14x20 mm body).