36 Mbit NoBL™ synchronous SRAM — 167 MHz pipeline, 3.4 ns access
It eliminates the dead cycle between read and write turns on a common data bus, sustaining back-to-back throughput at 167 MHz. The 3.4 ns access time keeps timing closure manageable on a moderate-speed memory controller — no exotic board layup needed for a single-chip buffer. Memory interface is parallel, supply runs from 3.135 V to 3.6 V, and the industrial temperature grade (-40°C to 85°C) suits base-station line cards, telecom line buffers, and DSP scratchpad memory where the ambient stays inside a ventilated enclosure.
NoBL™ bus — why the dead cycle disappears
Conventional synchronous SRAMs insert one idle clock when switching from read to write on the same data bus. The NoBL™ pipeline lets the next command start on the very next rising edge, so a 167 MHz bus is not starved by bus-turnaround overhead.