Dual-port asynchronous SRAM for shared-memory arbitration
The CY7C146-25JXCT is a 16Kbit dual-port asynchronous SRAM organized as 2K x 8, allowing simultaneous read/write access from two independent buses without bus-turnaround dead cycles. Its 25 ns access time sets the timing budget for arbitration logic in shared-memory systems.
25 ns access time and supply range
Access time is 25 ns for both read and write cycles, with write cycle time of 25 ns per word or page. Operating supply range is 4.5V to 5.5V, a legacy 5V logic level that requires level translation in mixed-voltage designs.
Obsolete – secondary-market sourcing
The CY7C146-25JXCT is marked Obsolete by Infineon Technologies. Sourcing is available through independent distribution; quote to order against BOM quantity.
52-PLCC footprint and commercial temperature grade
Packaged in a 52-PLCC (19.13 mm x 19.13 mm) with J-leads for surface-mount assembly.