36Mbit synchronous SDRAM — 133 MHz, 1M x 36
The CY7C1441KV25-133BZXI is a 36Mbit synchronous SDRAM organized as 1M x 36, clocked at 133 MHz with a 6.5 ns access time. The 1M x 36 width suits 32-bit data buses with parity or ECC overhead — the extra four bits per word let the controller store a parity nibble or ECC syndrome without a second chip.
Housed in a 165-ball LBGA (15x17 mm), the package demands a multi-layer PCB with controlled-impedance traces for the 133 MHz clock and data lines. The 1.0 mm ball pitch is routable on standard 4-layer stack-ups, but the 36-bit-wide bus needs careful signal-length matching to meet setup-and-hold margins at speed.
We source it against an RFQ — lot traceability and date-code verification are part of the quote process, and the availability picture is confirmed at quote time.