It runs on a 133 MHz clock with a 6.5 ns access time, operating from a 3.135 V to 3.6 V supply.
133 MHz clock, 6.5 ns access — timing margin for the bus
The 133 MHz clock yields a 6.5 ns access time. The synchronous SDR architecture avoids dead cycles on back-to-back reads.
Obsolete — sourcing reality for the BOM line
The CY7C1441AV33-133AXI is officially obsolete per Infineon's lifecycle status. No successor part number is listed in the official record. If your design can tolerate a different density or speed bin, a pin-compatible sibling in the same 100-LQFP footprint may exist — but no direct replacement is documented.
Package and rework — 100-LQFP, 14x20 mm body
The 100-LQFP (14x20 mm) is a standard fine-pitch surface-mount package. Pin 1 is marked by a chamfered corner and a dot on the top face.