36Mbit QDR II SRAM — 300 MHz, 1.7–1.9 V, 165-FBGA
The CY7C1426AV18-300BZXC is a 36 Mbit Quad Data Rate (QDR) II synchronous SRAM organized as 4M × 9 bits, operating at a 300 MHz clock frequency with a parallel interface. The 1.7 V to 1.9 V supply range aligns with low-voltage memory buses common in networking and telecom line-card designs. Packaged in a 165-ball LBGA (15 × 17 mm), the device is surface-mount and supplied in tray format.
QDR II bus architecture and throughput
QDR II architecture delivers four data words per clock cycle — two on the rising edge and two on the falling edge of both the K and K# clocks — yielding a peak data rate of 1.2 Gbps per I/O pin at 300 MHz. This burst-oriented interface is designed for applications requiring high random-access throughput with separate read and write ports, eliminating bus-turnaround cycles. The 4M × 9 organization provides a 9-bit-wide data path (8 data bits plus one parity/ECC bit), commonly used in packet-buffer and lookup-table designs where the extra bit supports error detection without external logic.
Lifecycle status and sourcing
Infineon lists the CY7C1426AV18-300BZXC as Obsolete. No pin-compatible direct replacement from the original manufacturer is documented. For existing BOM lines, the 165-FBGA footprint and 1.7–1.9 V supply rail are the critical fit parameters.