QDR II architecture and why it matters for your bus
The CY7C1425AV18-167BZXC is a 36 Mbit Quad Data Rate (QDR) II synchronous SRAM organized as 4M x 9. QDR II transfers data on both rising and falling edges of the clock, effectively doubling throughput per pin without increasing the core clock rate — the 167 MHz clock delivers 334 million data transfers per second on the read and write ports independently.
Obsolete — what that means for your BOM line
Infineon lists this part as Obsolete. For existing designs, this part is sourced through independent distribution channels — quantities are lot-specific and confirmed at RFQ.
Package, supply, and temperature grade
The supply range is 1.7 V to 1.9 V — the core and I/O share this single rail, so the board's 1.8 V rail must stay within that window under load.