Obsolete — last-time-buy sourcing reality
The CY7C1418JV18-300BZXC: Availability is lot-specific; quantities and date codes are confirmed at RFQ time.
36Mbit DDR II SRAM — 300 MHz clock, 2M x 18 organization
36Mbit synchronous DDR II SRAM organized as 2M words by 18 bits. The 300 MHz clock rate delivers double-data-rate transfers on each clock edge — the effective data rate is 600 MT/s on the parallel bus. Operates from a 1.7V to 1.9V core supply and uses a parallel memory interface. The 0°C to 70°C temperature range suits commercial equipment — telecom line cards, network switches, and test gear that stay in a controlled ambient.
Package and board-fit note
Housed in a 165-ball LBGA (15x17 mm FBGA per the supplier device package). Surface-mount only — the 0.80 mm ball pitch demands a multi-layer PCB with microvia fan-out under the BGA footprint. Shipped in Tray format — not tape-and-reel. For pick-and-place assembly, trays require a feeder change or manual loading; factor this into the line setup if the rest of the BOM runs on reels.