Skip to main content
Log in
Infineon Technologies CY7C1414AV18-250BZC — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1414AV18-250BZC QDR-II SRAM, 36Mbit, 250 MHz

MPNCY7C1414AV18-250BZC
Obsolete

Infineon Technologies CY7C1414AV18-250BZC synchronous QDR-II SRAM, 36Mbit (1Mx36), 250 MHz clock, 1.7-1.9 V, 165-FBGA tray, 0°C to 70°C.

Infineon Technologies CY7C1414AV18-250BZC datasheet (PDF)
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1414AV18-250BZC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage1.7V ~ 1.9V
Frequency250 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, QDR II
Memory size36Mbit
Memory formatSRAM
Case165-LBGA
Memory organization1M x 36

Product details

QDR-II SRAM at 250 MHz — the bandwidth ceiling

The CY7C1414AV18-250BZC is a 36 Mbit synchronous QDR-II SRAM organized 1M×36, clocked at 250 MHz on a 1.7–1.9 V core supply. The QDR-II architecture delivers two data words per clock cycle on separate read and write ports — at 250 MHz the interface sustains 18 Gbit/s of simultaneous read-write bandwidth, which is the figure that drives the fit in high-throughput packet buffers and traffic managers.

Obsolete — the sourcing reality for this part

Infineon lists the CY7C1414AV18-250BZC as Obsolete. A board spin is required if migrating to a different QDR-II density or package variant.

Package and thermal context for the 165-FBGA

The 1.7–1.9 V rail is tight; the board design must keep VDD ripple below 50 mV at the BGA balls to avoid setup/hold timing violations at 250 MHz.

Frequently asked questions

What is the memory organization and clock speed of CY7C1414AV18-250BZC?

It is a 36 Mbit QDR-II SRAM organized 1M×36 with a 250 MHz clock. The dual-port architecture delivers two data words per cycle on separate read and write buses.