What this QDR II SRAM does on the board
It clocks at 300 MHz and organizes the memory as 2M x 18 bits. The QDR II interface eliminates dead cycles on back-to-back reads and writes — the bus stays full every clock edge, which is what a high-throughput networking or test-equipment buffer needs.
At 300 MHz, the QDR II interface samples data on both clock edges.
