Infineon CY7C1413KV18-250BZC, 36 Mbit QDR-II synchronous SRAM, 250 MHz clock, 1.7–1.9 V supply, 2M x 18 organization, 165-LBGA tray pack, commercial 0°C to 70°C.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 1.7V ~ 1.9V |
| Clock frequency | 250 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, QDR II |
| Memory size | 36Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 2M x 18 |
The CY7C1413KV18-250BZC is a 36 Mbit QDR-II synchronous SRAM, organized 2M x 18 and clocked at 250 MHz. QDR-II architecture separates read and write data ports, eliminating bus-turnaround dead cycles.
No official L* successor or Infineon-qualified cross-reference appears in the current ledger. Sourcing paths are limited to remaining allocation, OEM excess, or open-market inventory — authenticity verification and traceability documentation are the buyer's responsibility in each case.
The Cypress QDR-II architecture requires the VDDQ supply to stay within the 1.7–1.9 V window throughout the clock cycle. At 250 MHz the voltage-eye is narrow; your 1.8 V nominal rail must hold within ±100 mV under all load conditions. A regulator with tight line/load regulation and low output noise is the design constraint — not the SRAM spec itself.