Dual-port async SRAM — 25 ns access, 1K×8 mailbox
The Cypress CY7C141-25JXC is a dual-port asynchronous SRAM organized 1K x 8, providing 8 Kbit of shared memory accessible from two independent ports with separate address, data, and control lines. Supply range is 4.5 V to 5.5 V, and the part is specified for commercial temperature (0°C to 70°C).
Obsolete — last-time-buy passed, surplus channel only
The CY7C141-25JXC is officially obsolete. No last-time-buy window remains from Cypress (now Infineon). available via RFQ confirmation through independent distribution is date-code-limited and should be verified for authenticity and proper storage.
In a dual-port system, both ports must arbitrate for the same memory array.
1K x 8 organization — sizing the shared buffer
With 8 Kbit organized as 1K x 8, this part is a small mailbox or register file, not a bulk data buffer. Typical use cases include passing command/status words between two processors or storing a small look-up table accessible from both sides. The 25 ns write cycle time (word/page) matches the read access, so back-to-back writes at full speed are possible without extra dead cycles.