18Mbit synchronous SRAM for cache and buffer applications
The CY7C1383KV33-133AXCT is an 18Mbit synchronous SDR SRAM organized as 1M x 18 bits. It runs at a 133 MHz clock with a 6.5 ns access time.
133 MHz clock and 6.5 ns access — timing margin for the bus
The 133 MHz clock defines the pipeline rate for back-to-back reads and writes. The 6.5 ns access time is the window from clock edge to valid data on the bus.
Commercial temperature grade — indoor use only
The 0°C to 70°C operating range limits this part to commercial-grade systems.