133 MHz synchronous SRAM — 512K×36 in a 165-ball BGA
The CY7C1381D-133BGXC: That 36-bit data bus makes it a natural fit for 32-bit processor systems with parity or ECC coverage — the extra four bits serve as byte parity lanes without stealing data bandwidth. The commercial temperature grade (0 °C to 70 °C) limits it to indoor, controlled environments — no cold-start or engine-bay duty.
Package and board-fit realities
Housed in a 165-ball LBGA (13×15 mm body per the supplier device package), the 1.0 mm ball pitch demands a four-layer PCB minimum for fan-out — two-layer boards cannot route the inner rows. The surface-mount footprint is standard for this class of synchronous SRAM; the same ball-out is shared across the CY7C1381D family, so a layout validated for one speed grade carries over to this 133 MHz variant. Supplied in tray packaging — not tape-and-reel. For volume production, factor in tray-to-reel conversion or pick-and-place from tray feeders.
Infineon lists the CY7C1381D-133BGXC as obsolete. Quantities are lot-specific and confirmed at RFQ; no stock-holding claim is made here.