Obsolete — BOM-fit and sourcing reality
The CY7C1381D-133AXIT: The 18Mbit synchronous SDR SRAM with 512K×36 organization, 133 MHz clock, and 6.5 ns access time was designed for high-performance cache and buffer applications in networking, telecom, and industrial controllers. The -40 to 85°C industrial temperature grade suited it for outdoor or unconditioned environments.
Parametric profile and package
The 100-LQFP package with a 14×20 mm body is a standard footprint for synchronous SRAMs of this density. The 3.135–3.6 V supply rail is typical for 3.3 V nominal SRAM families — the 0.465 V tolerance window means the supply must be regulated within ±7% of 3.3 V to stay in spec. At 133 MHz, the parallel memory interface delivers a burst data rate of 532 MB/s (32-bit bus at double data rate per clock edge). The 6.5 ns access time sets the minimum read-to-data-valid window from the address strobe.