18 Mbit synchronous SRAM — 133 MHz, 512K x 36
The CY7C1381D-133AXCT: This is a single-data-rate (SDR) synchronous SRAM, meaning it transfers one data word per clock cycle, suited for cache, buffer, and high-speed memory applications in networking, telecom, and test equipment where deterministic access latency matters.
The 133 MHz clock rate sets the maximum data throughput at 133 million 36-bit words per second. The 6.5 ns access time is the delay from address assertion to data valid on the outputs; in a synchronous system this defines the setup/hold window relative to the clock edge. For a design targeting 133 MHz operation, the 6.5 ns access gives roughly one clock cycle of address-to-data latency, which is typical for this speed grade. If your system runs at a lower clock rate, the part will still meet timing with margin, but the 133 MHz rating is the ceiling for guaranteed operation.
This means Infineon has discontinued production and no further last-time-buy windows are open. The part is no longer available through authorized franchised channels. Buyers should verify stock position and lead time before committing the BOM line.
Package and footprint — 100-TQFP (14x20)
The 100-TQFP package measures 14 mm x 20 mm with a 0.5 mm pitch. It is a surface-mount, leaded package suitable for reflow soldering. The supplier device package is specified as 100-TQFP (14x20), which matches the standard JEDEC outline for 100-pin thin quad flat packs. The tape-and-reel variant (TR suffix) is intended for automated pick-and-place assembly; if hand-placing or prototyping, the tray or tube variant may be preferred.