Infineon lists the CY7C1380C-167AC as Obsolete.
Memory density and bus width
Organised as 512K words × 36 bits, the CY7C1380C-167AC delivers 18 Mbit of synchronous SRAM. The 36-bit-wide data bus suits processors or ASICs that need a single-chip 32-bit data path plus parity or ECC coverage on the same die — no external byte-lane muxing required.
Clock rate and access timing
The synchronous SDR interface latches address and control on the rising clock edge, so the access time is the delay from clock edge to valid data out — this sets the read-cycle timing margin for the controller. At 167 MHz the clock period is 6 ns, leaving roughly 2.6 ns of setup/hold budget after the 3.4 ns access for the receiving logic.
Housed in a 100-lead LQFP with a 14 mm × 20 mm body. Surface-mount assembly; supplied in tray format.