133 MHz NoBL synchronous SRAM — 18 Mbit, 1M x 18
The CY7C1373KV33-133AXI: The 6.5 ns access time means the first word appears on the data bus within one clock cycle of the address being latched — no wait states for the initial read. The 1M x 18 organization suits 18-bit DSP data paths, packet-processing buffers, and wide-word cache applications where a 16-bit or 18-bit word is the natural data unit. The parallel interface eliminates serialization overhead that SPI or QSPI memories introduce at the controller boundary.
Supply voltage and temperature grade
The 100-TQFP (14x20 mm) package uses a 0.5 mm pitch — routable on a standard 4-layer PCB without microvias or blind vias.
Active lifecycle and compliance
ROHS3 compliant (no exemptions), which covers EU RoHS and similar global restrictions without a waiver.