18 Mbit NoBL synchronous SRAM for high-throughput cache and buffer designs
The CY7C1373D-100AXCT: It operates with a 100 MHz clock and delivers an 8.5 ns access time, eliminating dead cycles between read and write turns on a shared bus. This makes it suited for high-throughput applications such as network packet buffers, cache memory in telecom line cards, and DSP scratch-pad storage where back-to-back bus transactions are the norm.
The CY7C1373D-100AXCT is officially obsolete per the manufacturer's lifecycle status.
Housed in a 100-LQFP package with a supplier device package of 100-TQFP (14x20 mm), this is a surface-mount device intended for parallel interface routing. The 14x20 mm body and 0.5 mm pitch are standard for this density class; the footprint matches other Cypress 100-pin NoBL SRAMs in the same package, easing second-source qualification on the board layout.