18 Mbit synchronous SRAM for high-throughput buffer designs
It clocks at 200 MHz with a 3 ns access time, running from a 3.135 V to 3.6 V supply. The parallel interface and 100-LQFP package (14×20 mm body) target networking buffers, DSP scratchpads, and telecom line-card applications where back-to-back throughput matters.
A 3 ns access time at 200 MHz means the SRAM can deliver data within one clock cycle of the address being latched, assuming the pipeline depth is accounted for. In practice, this gives the controller a tight timing budget for setup and hold on the data bus — critical when the part is used in a high-speed cache or FIFO buffer where every nanosecond of margin affects system stability.
NoBL architecture — no dead cycles
The NoBL™ architecture switches between read and write operations on consecutive clock edges without idle cycles. This can increase throughput compared to conventional synchronous SRAM that inserts a turnaround cycle.