18 Mbit synchronous SRAM with 3.4 ns access at 167 MHz
It operates with a parallel interface at a 167 MHz clock frequency and delivers a 3.4 ns access time, making it suitable for high-throughput buffer and cache applications in networking, telecom, and test equipment that require deterministic read/write latency. The device runs from a 2.375 V to 2.625 V supply and is housed in a 100-LQFP package (100-TQFP 14x20 mm footprint).
The 167 MHz clock rate supports pipelined read/write operations without wait states in a synchronous bus. The 3.4 ns access time from clock edge to data valid sets the timing closure budget for the controller interface; at this speed, PCB trace length matching and signal integrity on the parallel bus become critical. The NoBL™ architecture eliminates dead cycles between read and write turns, sustaining back-to-back throughput at the full clock rate.
Cypress (now part of Infineon) no longer manufactures this device in volume.
2.5 V supply and commercial temperature range
The supply range of 2.375 V to 2.625 V aligns with 2.5 V logic families and DDR memory interfaces. For extended-temperature or automotive applications, a different temperature-grade variant or a different part family would be required.