18Mbit synchronous SRAM at 200 MHz — NoBL pipeline for FPGA cache
The CY7C1372D-200AXC is a 18Mbit synchronous SRAM organized as 1M x 18, part of Cypress's (now Infineon) NoBL series. The NoBL (No Bus Latency) architecture eliminates dead cycles between read and write operations — the bus switches direction on consecutive clock edges without an idle cycle, which matters for FPGA block RAM expansion or high-throughput data buffers where every clock counts. Rated for a 200 MHz clock with a 3 ns access time, the part delivers a 5 ns cycle time in a standard synchronous pipeline. The 0°C–70°C commercial temperature grade limits this to indoor, controlled-environment equipment; no industrial or automotive derating is offered.
100-TQFP footprint and rework considerations
Housed in a 100-lead TQFP with a 14x20 mm body (EIAJ standard), the 0.5 mm pitch requires a controlled reflow profile — peak temperature 260 °C per J-STD-020 for a moisture-sensitive level 3 part. The exposed pad on the underside is not a thermal pad on this variant; the die is bonded to the leadframe, so the primary heat path is through the leads. Supplied in tray format — the 100-TQFP tray holds 90 units per JEDEC standard tray. No tape-and-reel option is listed, so the part is not suited for high-volume pick-and-place without a tray feeder.
Infineon lists the CY7C1372D-200AXC as Obsolete. No authorized-distributor stock is maintained by Infineon for this order code. For sustainment programs, the 200 MHz speed grade and 3.3 V I/O are the binding constraints. The 100-TQFP footprint is standard, so a re-spin using a current-generation synchronous SRAM in the same package is feasible if the NoBL bus protocol is not required.