18Mbit synchronous SRAM for high-throughput cache and buffer applications
The CY7C1372D-167AXIT: This parallel-interface memory is designed for high-throughput data buffering and cache applications where the NoBL architecture eliminates dead bus cycles between read and write operations.
The CY7C1372D-167AXIT is marked obsolete by Infineon. For sustainment programs or repair of existing designs, this part is sourced through independent distribution channels.
Package and board-fit for the 100-TQFP footprint
Housed in a 100-lead LQFP (14x20 mm body), the supplier device package is 100-TQFP (14x20). The 0.5 mm pitch requires careful fan-out on the PCB — a four-layer board is typical to route the 18-bit data bus plus address and control lines without excessive via stubs. The tape-and-reel packaging suits automated pick-and-place assembly.
The NoBL series eliminates the turnaround cycle between reads and writes — consecutive read-after-write or write-after-read operations complete on every clock edge at 167 MHz. The 3.4 ns access time from clock rise means the data is valid at the output pins within one clock period at speed, leaving margin for board trace delay and setup time at the receiving FPGA or ASIC. With 1M x 18 organization, the part provides 18 bits per address — useful for 18-bit DSP data paths or as a 16-bit wide memory with two parity bits. The parallel interface demands 18 data lines plus address and control, so the PCB layout must match trace lengths within the group to avoid skew at 167 MHz.