Clocked at 167 MHz with a 3.4 ns access time, it operates from 3.135 V to 3.6 V with a parallel memory interface.
Military temperature range — what it means for deployment
The case temperature spec means the die junction tracks the package surface.
NoBL architecture — why the bus turnaround matters
Standard synchronous SRAMs insert a dead cycle when switching from read to write (or write to read), wasting a clock edge. The NoBL pipeline eliminates that gap, allowing back-to-back transactions at full 167 MHz throughput. For a 512K x 36 memory bus feeding a DSP or FPGA, that means no pipeline stalls on mixed read/write sequences—critical in radar signal processing or real-time control loops where every cycle counts. The trade-off: NoBL parts use a slightly different control logic (ADV/LD rather than simple chip-enable timing), so verify the controller interface before dropping it into a legacy socket designed for a pipelined SRAM without NoBL.
Listed as Active on the manufacturer status, but the eol_hot lifecycle stage flags this part as approaching end-of-life.