18 Mbit NoBL™ synchronous SRAM for high-throughput data paths
It eliminates the dead cycle between read and write operations, sustaining full back-to-back throughput at a 167 MHz clock rate. The 3.4 ns access time keeps read latency within a single cycle for most host controllers. This part targets networking equipment, baseband processors, and high-speed data buffers where bus turnaround overhead directly limits line rate.
167 MHz clock and 3.4 ns access — timing budget for the bus
The 167 MHz clock sets the maximum data rate for the parallel interface. The 3.4 ns access time keeps read latency within one cycle for most host controllers.