18 Mbit NoBL synchronous SRAM — 167 MHz pipeline, 3.4 ns access
It operates from a 2.5V supply rail (2.375V–2.625V) and clocks at 167 MHz with a 3.4 ns access time from clock edge. The NoBL architecture eliminates dead cycles between read and write turns on the same port, sustaining full pipeline throughput in back-to-back transactions — a fit for high-bandwidth data buffers in networking line cards, telecom switches, and test equipment where the bus must never stall.
Package and supply — 165-ball FBGA, 2.5V rail only
The supply voltage is strictly 2.5V nominal; the 2.375V–2.625V window means the part cannot share a 3.3V or 1.8V plane without a dedicated regulator.
Obsolete — sourcing via independent distribution
Infineon lists the CY7C1370DV25-167BZC as Obsolete. For BOM lines that still require this exact order code, supply is limited to surplus and broker-channel inventory — sealed reels with consistent date codes are the preferred sourcing grade.
