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Infineon Technologies CY7C1370D-200AXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1370D-200AXI 18Mbit NoBL SRAM, 200 MHz

MPNCY7C1370D-200AXI
Obsolete

Infineon CY7C1370D-200AXI, NoBL™ series, 18Mbit Synchronous SRAM, 200 MHz clock frequency, 3 ns access time, 512K x 36 organization, Parallel interface, 3.135V~3.6V supply, -40°C~85°C, 100-LQFP, Surface Mount, Tray.

Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1370D-200AXI specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Voltage3.135V ~ 3.6V
Frequency200 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3 ns
Memory size18Mbit
Memory formatSRAM
Case100-LQFP
Memory organization512K x 36

Product details

High-speed synchronous SRAM with NoBL architecture

200 MHz clock and 3 ns access — what they mean for timing closure

The 200 MHz clock frequency sets the maximum operating rate for the memory interface. At this speed, the 3 ns access time defines the window from clock edge to valid data on the bus. For a system architect, this means the FPGA or ASIC controller must budget for a 3 ns tCO plus board trace delay and still meet setup time on the receiving end. The 512K x 36 organization provides 18 Mbit of storage with a 36-bit wide data path, suitable for 32-bit plus parity or ECC applications.

The 100-TQFP (14x20 mm) package is a standard fine-pitch surface-mount footprint with 0.5 mm lead pitch.

Infineon has classified the CY7C1370D-200AXI as Obsolete. There is no pin-compatible direct replacement from Infineon's current SRAM portfolio; any substitution would require a board respin and revalidation of the memory controller timing.

Frequently asked questions

What is the replacement for CY7C1370D-200AXI?

Infineon has not published a direct pin-compatible successor for the CY7C1370D-200AXI. Any replacement would require a board-level redesign and memory controller retiming. For existing designs, the only option is sourcing the original part through the surplus channel.

What is the access time of CY7C1370D-200AXI?

The access time is 3 ns, measured from the active clock edge. At a 200 MHz clock rate, this gives a 5 ns cycle period, so the 3 ns access leaves 2 ns for address-to-clock setup and board delay before the next cycle.